1. Field of the Invention
The present invention generally relates to multi-stage, pipelined subranging analog-to-digital converters and, more particularly, to a system for correcting conversion errors in multi-stage pipelined, subranging analog-to-digital converters.
2. Description of the Prior Art
A subranging analog-to-digital converter is described by A.G.F. Dingwall and W. Zazzu in "An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE J. Solid-State Circuits, Vol. SC-20, pp. 1138-1143, December 1985, and S.H. Lewis and P.R. Gray in IEEE J. Solid-State Circuits, Vol. SC-22, No. 6, pp. 954-961, December 1987.
In the so-called "digital correction" method described by S.H. Lewis and P.R. Gray, supra, the interstage gain is made one half of the conventional amount, i.e., 2.sup.L-1 for a stage that uses L-bit analog-to-digital (A/D) and digital-to-analog (D/A) converters. The residual signal thus spans only half of the range of the subsequent stage. In this circumstance, errors in the A/D converter of any stage, up to .+-.1/2 of a least significant bit (LSB), can be accommodated. Such errors will cause the amplified residual signal to fall either above or below the expected range and can be corrected by either incrementing or decrementing the L-bit A/D converter code for the prior stage respectively. Although this method is very simple, it cannot correct any error in the D/A converter, or in the gain stage, and it is not sufficient for high resolution (i.e., resolution above 9 bits).
Use of a radix 1.85, instead of radix 2, along with digital coefficients to implement a corrected output signal is also known. This technique is described by S.G. Boyacigiller et al. in "An Error Correcting 14b/20.mu.s CMOS A/D Converter", ISSCC Dig. Tech. Papers, pp. 62-63, February 1981. This approach is capable of correcting for component matching errors and gain errors. However, its inability to accommodate any nonlinearity in the gain stages or elsewhere limits its practicality in implementing high resolution converters.
Subranging analog-to-digital converters are attractive for high-speed operation since they are almost comparable in speed to a flash converter, but use far less hardware. For example, an N-bit flash converter makes use of 2.sup.N -1 comparators, while the same resolution in an L stage subranging architecture requires only L(2.sup.N/L -1) comparators. Unfortunately, efforts to obtain high resolution are hampered by practical circuit nonidealities such as component mismatching, nonlinearity, offset, noise, etc. In the case of a subranging A/D converter in particular, accuracy is limited by the degree of linearity of the A/D and D/A converters in the first stage. Resolution at accuracy levels beyond the limits of the nonideal components mentioned above, however, is obtainable by use of this invention.